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AR# 23850

LogiCORE RapidIO v4.1 - Release Notes and Known Issues for 9.1i IP Update 1

Description

This Release Note and Known Issues Answer Record is for the RapidIO v4.1 released in 9.1i IP Update 1 and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 24307).

A patch (Rev 1) is available to apply for this release to resolve several known issues below. See (Xilinx Answer 25118).

Solution

General Information

Starting with v4.1 of the LogiCORE Serial RapidIO solution, the sRIO PHY, RIO Logical IO, and RIO Design Environment Cores have been integrated into a single end-point solution.

(Xilinx Answer 24888) Migrating Serial RapidIO design from v3.1 to v4.1

New Features in v4.1

- Support added for Virtex-5 LXT/SXT.

- Support added for ISE 9.1i.

- The core MGTs have been extracted out of the netlist and are now instantiated in a PHY-level MGT wrapper to enable users to tailor them more easily.

- NO_DATA input has been added to TRESP port to support sending unsupported packet types without data.

- Enhanced user design allows the end-point to source traffic.

Bug Fixes in v4.1

CR 234167: When Rx buffer throttles the PHY core, packets might not be discontinued properly

CR 430681: MASTER_ENABLE bit not working

(Xilinx Answer 24500) Corrupted or repeated packets occur on data

(Xilinx Answer 24501) The core netlist cannot be loaded into PlanAhead

(Xilinx Answer 24527) Repeated packet can be seen upon RETRY

(Xilinx Answer 24498) Logical Layer- Full 16-bit device ID is not usable

(Xilinx Answer 24497) Transmit port can result in lock-up

(Xilinx Answer 24499) Packets corrupted in the buffer

(Xilinx Answer 24844) The buffer can go into a permanent stall state if the current packet is discontinued and there is no lnk_next_fm change

Known Issues in v4.1

General

(Xilinx Answer 24966) Fixed in Rev1 patch - The CORE Generator window or ISE Project Navigator might close when generating Serial Rapid IO v4.1 due to the missing license file

(Xilinx Answer 24994) Fixed in Rev1 patch - The Device ID entered though the GUI is ignored. CRS register will contain "OO" or "0000" as Device ID

(Xilinx Answer 24986) Fixed in Rev1 patch - Invalid TTYPE value in the iresp_handler.v file

(Xilinx Answer 24987) CORE Generator fails to generate the core when illegal component names are used

(Xilinx Answer 24967) Signal inversion needed when targeting ML523 rev D board

(Xilinx Answer 25318) Design Example provided with the core might not work if you modify "ireq_gnerator.v" file to add other packet transactions

(Xilinx Answer 25319) Using the example design, ireq ports are not connected properly

(Xilinx Answer 29263) Buffer Design provided with the core might duplicate or corrupt packets

(Xilinx Answer 30054) CAR value incorrect

(Xilinx Answer 30323) Re-initialization is not forced following a change to Port Width Override

Physical Layer

(Xilinx Answer 25088) For Virtex-4, RX and TX, PLLs might fail to lock or exhibit excess jitter due to incorrect MGT settings

(Xilinx Answer 24837) Stomped packet incorrectly sent after Restart-from-Retry control signal causing protocol error (Packet Not Accepted)

(Xilinx Answer 24838) Fixed in Rev1 patch - The x1 Core is unable to train when connected to x4 Core when targeting Virtex-5 or Virtex-II Pro

(Xilinx Answer 24970) A control symbol which has been scheduled into the transmit pipeline might be lost if reinitialization is forced

(Xilinx Answer 24982) A Restart-from-Retry control symbol followed immediately by a Link Request control symbol might cause the core to issue a Packet Not Accepted control symbol with a reserved cause field value

(Xilinx Answer 29233) On the receive (RX) side, AckID misalignment can be seen

(Xilinx Answer 30023) x4 Core can train down to x1 using lane 0, but not to other lanes

(Xilinx Answer 30314) Virtex-4, x4 Core might intermittently train down to x1 due to MGT lock signal issue.

Logical Transport Layer

(Xilinx Answer 24968) Logical Layer Receive side cannot handle stalls on incoming Rx packets; data corruption might be seen

(Xilinx Answer 30320) Messaging packet has incorrect treq_byte_count

(Xilinx Answer 29936) Maintenance RESEPONSE packet has incorrect source device ID

(Xilinx Answer 30322) Missing EOF or missing packet on target request interface when sending 8-byte SWRITE

Known Issues in v3.1

Serial Rapid IO v3.1 is now obsolete; you must upgrade to the latest core available through the latest IP Update. For existing known issues in Serial Rapid IO v3.1, see (Xilinx Answer 22319).

AR# 23850
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article