What are the limitations or restrictions associated with utilizing Cadence NCSIM simulator?
- As of EDK 8.2.01i, Xilinx does not fully support any version prior to IUS5.7 of NCSIM for RTL level simulation (in VHDL and Verilog).
- This issue is caused by a limitation in the older versions of NCSIM.
- The problems appear if you have installed ISE 8.2.02i (ISE 8.2i Service Pack 2) or a newer version of the ISE 8.2i design tools.
- You will receive errors at the library compile step (Simulation Library Compilation Wizard or COMPEDKLIB). The log file will indicate NCSIM internal errors for certain cores in the XilinxProcessorIPLibrary. The errors appear in the log file but might not be reported in the Simulation Library Compilation Wizard (COMPEDKLIB) GUI.
- Use IUS 5.7 (not available on Windows platforms)
The library compile step does not generate errors. Xilinx is currently investigating whether or not there are other issues if this version of IUS is used. This Answer Record will be updated with more information as necessary.
You will have to use the -lib_binding option for ncelab. See (Xilinx Answer 19446) for more on this ncelab option.