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AR# 23862

MIG Virtex-4 FPGA - Changes to read capture timing for Virtex-4 FPGA memory controllers after MIG v1.5


Read capture timing for MIG Virtex-4 FPGA memory controller designs must take into account pattern-related jitter through the IDELAY component. This is represented as tIDELAY_JIT in the Virtex-4 FPGA data sheet and is specified as a maximum of 12 ps peak-to-peak per IDELAY tap used for a nonperiodic input pattern.


As a result of this additional factor in the Virtex-4 FPGA Direct Clocking read timing budgets, the maximum memory clock frequencies have decreased from those specified in previous MIG releases. These decreased frequencies are reflected in MIG releases since MIG v1.5. The updated maximum frequencies (based on the fastest memory speed grades available) for each interface supported by MIG for Direct Clocking designs are summarized below. The timing numbers represent absolute worst case conditions, but many boards might not fall into this category because of the PCB traces and memory components that are used. Designers should evaluate existing boards with this in mind.  


Maximum Frequency Comparison
Maximum Frequency Comparison


The maximum frequencies for several of the interfaces did not change because existing slack in the read timing analysis was able to absorb the additional IDELAY pattern jitter. 


NOTE: The Virtex-4 FPGA SERDES design still supports operation up to 300 MHz (using a Virtex-4 -12 device, using highest available memory speed grade). The SERDES employs a different read data capture architecture that impacts timing less than in the Direct Clocking case with the additional IDELAY pattern jitter. You should use the SERDES design for new DDR2 designs running above 210 MHz.

AR# 23862
Date 05/20/2014
Status Archive
Type General Article
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