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AR# 23871

8.2i MAP - What are route-thrus?


Keywords: route, thru, mrp, carry, MUX, .mrp

In the MAP report (.mrp) for any FPGA design, the Design Summary contains information on route-thrus, as in the following example:

Total Number 4 input LUTs: 986 out of 12,288 8%
Number used as logic: 919
Number used as a route-thru: 67

What does the route-thru count represent?


Route-thru LUTs are used in all FPGA families to access internal slice points when direct access is not available or less efficient. The reasons for using a route-thru include:

- Access to some internal components are only available via the output of a LUT. If no combinatorial logic functionality is required before accessing this point, the LUT must still be consumed as a route-thru to get to this point. These components include the CYMUX (select pin) and the F5MUX.

- If a register must be accessed directly and the BX and BY pins (which can be used for direct access) are already used, the register must be accessed via route-thru.

For Virtex-5, the portion of the Design Summary that includes route-thrus is more extensive. Exclusive route-thrus are defined as LUTs that contain no logic, just a route-thru, and some LUTs contain both logic and route-thrus. The following is an example:

Number of Slice LUTs: 819 out of 19,200 4%
Number used as logic: 812 out of 19,200 4%
Number using O6 output only: 769
Number using O5 output only: 37
Number using O5 and O6: 6
Number used as exclusive route-thru: 7
Number of route-thrus: 113 out of 38,400 1%
Number using O6 output only: 39
Number using O5 output only: 69
Number using O5 and O6: 5

In the above example, 7 LUTs contain only route-thrus and no logic. 5 of them use both O5 and O6 outputs, and 2 use only one output. Therefore, the remaining 106 route-thrus (which each only use one output) share the LUT6 with other combinatorial logic that utilizes the other output.

Routing congestion does not factor in to the use of route-thrus reported in MAP, as the routing phase has not yet been completed at this point. It is rare for LUT resources to be required for routing paths in the Virtex and Spartan architecture families.
AR# 23871
Date 08/23/2006
Status Active
Type General Article
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