When using Message Signaled Interrupts (MSI), the MSI packet is generated inside the core by a configuration management module. This MSI TLP is then inserted into the transmit buffers shared by the user data path.
1) If the user fully loads a transaction layer packet (TLP) into the core and then toggles the interrupt pin (cfg_interrupt_n) to generate an MSI interrupt, will the MSI be queued behind the TLP?
2) If there are no TX buffers available, and the user is asserting trn_sof_n and trn_tsrc_rdy_n indicating it is waiting to generate a TLP (posted, completion, or non-posted) and is also signaling an interrupt, which packet gets priority when the buffer frees? Is it the user packet or the MSI?
1) Answer: If trn_teof_n comes on cycle n and the interrupt is toggled on cycle n or n+1, the TLP will be ahead of the MSI TLP in the outgoing queue inside the core. Note that normal packet ordering rules still apply once the packets are loaded into the transmit buffers. As indicated by the PCI Express specification, if the receiving link partner device indicates it cannot momentarily accept nonposted packets, posted and completion packets will be promoted around any nonposted packets. The MSI TLP is a posted packet, as it is a Memory Write TLP.
2) Answer: If the trn_tsof_n assertion is less than 4 cycles before acceptance (assertion of trn_tdst_rdy_n), the TLP wins. Otherwise, the MSI will be queued first. This is a result of the pipelining of the cfg_interrupt_n signal (4 stages of pipeline) inside the core. This 4-cycle pipeline of the cfg_interrupt_n signal is similar to version 3.2 of the PCIe core.