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AR# 23882

LogiCORE SPI-4.2 (POS-PHY L4) v8.1 - GUI will not allow a coe file to be loaded

Description

Loading a COE file for SPI-4.2 v8.1 Core gives the following error:

"Validation Failed: Invalid Radix in COE file-only 2, 10, 16 are valid"

Even a coe file that was properly loaded in the SPI-4.2 GUI for the v7.4 Core will not load in the v8.1 GUI.

Solution

This is an issue with COE file reader for SPI-4.2 v8.1 Core and is expected to be fixed in v8.2.

To work around this issue:

1. Generate the SPI-4.2 v8.1 Core without the COE file loaded.

2. Generate the SPI-4.2 v7.4 Core with the COE file loaded, using the same configuration as for the v8.1 Core.

3. In the UCF file generated from the v8.1 file, look for the calendar logic initialization section. There will be two, one for Sink and Source.

(UCF file is generated in the /example_design/ sub-directory of your project directory.)

Example:

######################################################################

# Initialize the calendar logic

# Sample initialization values are shown below, defaulting the calendar

# to a round-robin sequence.

######################################################################

# INST "v81_stat_pl4_src_top0/U0/cal0/cram/BlockRam" INIT_00 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;

# INST "v81_stat_pl4_src_top0/U0/cal0/cram/BlockRam" INIT_01 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;

# INST "v81_stat_pl4_src_top0/U0/cal0/cram/BlockRam" INIT_02 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;

# INST "v81_stat_pl4_src_top0/U0/cal0/cram/BlockRam" INIT_03 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;

# INST "v81_stat_pl4_src_top0/U0/cal0/cram/BlockRam" INIT_04 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;

# INST "v81_stat_pl4_src_top0/U0/cal0/cram/BlockRam" INIT_05 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;

# INST "v81_stat_pl4_src_top0/U0/cal0/cram/BlockRam" INIT_06 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;

# INST "v81_stat_pl4_src_top0/U0/cal0/cram/BlockRam" INIT_07 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;

# INST "v81_stat_pl4_src_top0/U0/cal0/cram/BlockRam" INIT_08 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;

# INST "v81_stat_pl4_src_top0/U0/cal0/cram/BlockRam" INIT_09 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;

# INST "v81_stat_pl4_src_top0/U0/cal0/cram/BlockRam" INIT_0A = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;

# INST "v81_stat_pl4_src_top0/U0/cal0/cram/BlockRam" INIT_0B = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;

# INST "v81_stat_pl4_src_top0/U0/cal0/cram/BlockRam" INIT_0C = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;

# INST "v81_stat_pl4_src_top0/U0/cal0/cram/BlockRam" INIT_0D = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;

# INST "v81_stat_pl4_src_top0/U0/cal0/cram/BlockRam" INIT_0E = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;

# INST "v81_stat_pl4_src_top0/U0/cal0/cram/BlockRam" INIT_0F = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;

4. Replace the above calendar initialization section of the v8.1 Core with the one from v7.4 UCF. Be sure to modify for both the Sink and Source core sections.

5. In your design, use all the files you have generated in v8.1 Core. Only the UCF file needs modification.

NOTE: "#" at the beginning of the UCF file indicates that the rest of the line is commented out. So be sure to uncomment appropriate lines as needed.

AR# 23882
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article