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AR# 23898

MIG v1.6 - README file for Virtex-4 DDR2 SDRAM Direct Clocking incorrect


Keywords: sim, DDR2, readme, MT47H256M4BT-37E

The "README.txt" file, located in mig_v1_6\data\dlib\virtex4\DDR2 SDRAM\Direct clocking\sim
, was not properly updated with the MIG v1.6 release. The updated contents are found below.


The sim folder contains sample test_bench files to simulate the designs in the ModelSim environment. This folder contains the memory model, test bench file, and required parameter file(s). Read the steps in this file before running the simulation.

To run simulation for this sample configuration, you must generate the RTL from the tool for the following GUI options:

Data_width : 8
Frequency : 200
HDL : Verilog / VHDL
Memory configuration : x4
DIMM/Component : Component
Memory Part No : MT47H256M4BT-37E
Depth : 1
ECC : disabled
Use DCM : Yes
No. of controllers : 1

1. After the design is generated, change the name of the top-level module name "mem_interface_top" in ddr2_test_tb.v file with the module name generated from the MIG tool.

2. Modify the memory module parameter file ddr2_parameters.vh (memory parameters) according to the memory you have chosen.

3. After the RTL is generated, create the ModelSim project file. Add all of the files from the RTL folder
to the project. Also, add the memory model, test bench, and glbl files from the sim folder.

4. Compile the design.

5. After successful compilation of the design, load the design using the following command:

vsim -t ps +notimingchecks -L ../Modeltech_6.1a/unisims_ver work.ddr2_test_tb glbl
Note : User should set proper path for unisim verilog libraries

6. After the design is successfully loaded, run the simulation and view the waveforms.

- To run simulation for different data widths and configurations, modify the test bench files with the right memory models and design files.
- You must manually change the frequency of the test bench for proper simulations.
AR# 23898
Date 04/06/2009
Status Archive
Type General Article