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AR# 23904

14.7 MAP/PAR - Will the Xilinx implementation tools give the exact same results with the exact same source files, system, and software version?


Will Xilinx implementation tools give the exact same results with the exact same source files, constraints, system, software version, etc.?


Yes, the Xilinx implementation tools (and XST) are designed to be deterministic, meaning that given the same design, software environment and tool options, the tools will reach the same result.

The platform used should not make a difference.

The software user issues that can cause a difference in results are:

  • Difference in source files
  • Difference in tool revision
  • Difference in tool options
  • Difference in environment variable settings
  • Difference in file date stamps (after copy/restore) affecting NGDBuild (use "-nt on" switch as work-around)

If all of these possible differences have been accounted for, differing results from two runs are considered a software defect and should be reported to Xilinx.

These problems are fixed when they are detected.

Typical problem areas are the following:

Cross platform differences - For example, a sorting algorithm used might result in a different order of processing on two different platforms (Windows and Linux) resulting in a different final result.

Both results are equally valid, and the relative quality of each result is subject to chance, much like choosing different cost table seeds for PAR.

MPPR results do not match Single pass results for the same cost table - This problem can result from the failure to properly reinitialize all variables between MPPR cost table runs.

Again, the relative quality is subject to chance.

Typically, single pass runs on the same machine are deterministic.

If differences are seen, the source of the difference can be traced to a specific application by comparing the log files for MAP (.mrp) and PAR (.par).

Compare the MAP summary information for differences.

The PAR placement pass checksum values (Xilinx Answer 15611) can be used to identify whether a particular placement pass generated the same results, and if not, determine where the two runs diverged.
AR# 23904
Date 12/04/2014
Status Active
Type General Article
  • FPGA Device Families
  • ISE Design Suite - 14