We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23936

8.2i TRACE/Timing Analyzer - Why is the clock skew always reported as zero?


My design is using MGT, and the RXRECCLK output is driving a BUFG. Then the BUFG's output drives the RXUSRCLK, RXUSRCLK2, and FPGA fabric. The received data register is clocked by the BUFG output as well. Because the clock delay from BUFG to RXUSRCLK is longer than BUFG to register, there should be negative clock path skew in the timing report. However, the timing analysis always shows clock path skew as zero. Why does this occur?


The problem occurs because the RXRECCLK clock network has not performed any skew analysis previously.

This problem has been fixed in the latest 8.2i Service Pack available at:

The first service pack containing the fix is 8.2i Service Pack 3.

AR# 23936
Date 01/18/2010
Status Archive
Type General Article