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AR# 23957

14.x Constraint - How do I constrain an input DDR signal when the clock is driven by a BUFR (DDR OFFSET)?

Description

How do I constrain an input DDR signal when the clock is driven by a BUFR?

Solution

If the clock drives an IBUFG, IBUF, write the constraint as follows:

New Method (Recommended)

#Create Period
NET CLK TNM_NET = CLK_GRP;
TIMESPEC "TS_CLK" = PERIOD CLK_GRP" 5 ns HIGH 50%;
#Create OFFSET constraint
TIMEGRP DATA_IN OFFSET IN = 1 BEFORE CLK RISING;
TIMEGRP DATA_IN OFFSET IN = 1 BEFORE CLK FALLING;

Old Method (Not Recommended)

#Create Period
NET CLK TNM_NET = CLK_GRP;
TIMESPEC "TS_CLK" = PERIOD CLK_GRP" 5 ns HIGH 50%;
#Create Groups
INST DATA_IN[*] TNM = DATA_IN;
TIMEGRP FF_RISING = RISING CLK_GRP ;
TIMEGRP FF_FALLING = FALLING CLK_GRP;
#Create OFFSET constraint
TIMEGRP DATA_IN OFFSET IN = 1 BEFORE CLK TIMEGRP FF_RISING;
TIMEGRP DATA_IN OFFSET IN = -1.5 BEFORE CLK TIMEGRP FF_FALLING;

However, if the clock drives a BUFG, you cannot use the input clock net name to define the RISING and FALLING timing group. You should use the output clock net from the BUFR for the RISING and FALLING timegroups.

AR# 23957
Date Created 09/04/2007
Last Updated 12/19/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 11
  • ISE Design Suite - 12
  • ISE Design Suite - 13
  • ISE Design Suite - 14