My design is stuck at Phase 5.30 in PAR. What is phase 5.30, and how can I avoid this problem?
Phase 5.30 is an extra clock placement phase that is called for difficult designs. Cases have been seen with very difficult designs where the placer appears to hang at this point. This problem can be avoided by area constraining global clock domains to clock regions so that no more that eight domains exist in any one region. For more information on this, see (Xilinx Answer 23036).
This problem has been fixed in the latest 8.2i Service Pack available at:
The first service pack containing the fix is 8.2i Service Pack 3.
The fix is to set a limit on this clock placement phase so that it will error out on infeasible designs rather than hanging.