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AR# 24014

LogiCORE SPI-4.2 (POS-PHY L4) v8.2 - Migrating from v8.1 to v8.2 (Migration Guide)

Description

This Answer Record shows how to migrate the SPI-4.2 Core from v8.1 to v8.2, and describes the signal changes made to the core. Every attempt was made to keep the constraints, input, and output signals consistent between versions. This Answer Record covers those modifications required to upgrade from v8.1 to v8.2.  

 

The following sections are included: 

 

- XCO parameter changes 

- Core Signal Changes  

- Wrapper File Changes 

- UCF and NCF File Changes

Solution

XCO Parameter Changes  

Following new parameters are introduced in v8.2 core: 

 

CSET generate_continuous_alignment_halt_pin=true 

CSET generate_advance_dpa_diagnostic_ports=true 

CSET read_mode=Full_Burst 

CSET sink_dedicated_idelayctrl_reset=true  

 

Please see User Guide for specific information. 

 

Core Signal Changes  

 

1) SrcBurstLen[9:0]: The width of the SrcBurstLen bus in the Source Core is increased to 10 (SrcBurstLen[9:0]) to support  

maximum unsegmented source core packet size of 16k bytes(SrcBurstLen) 

 

2) If "Generate Dedicated Input IDELAYCTRL Reset" option is selected from the GUI, the following optional signal 

is added to the v8.2 Sink Core: 

- SnkIdelayCtlRst (Input): Sink Dedicated IDELAYCTRL Reset. Active high signal that asynchronously resets all 

the IDELAYCTRL primitives instantiated in the Sink core. 

 

3) If "Generate Continuous Alignment Halt Pin" option is selected from the GUI, the following optional signal is added to the v8.2 Sink Core: 

- SnkCDPAHalt (Input): Phase Alignment DPA halt. Active high signals suspends the pointer adjustment or continuous DPA operation.  

 

4) If "Generate Advance DPA Diagnostic Ports" option is selected from the GUI, the following optional signals are 

added to the v8.2 Sink Core: 

- SnkDPADiagWin (Input): Phase Alignment DPA Diagnostics. Active high signal that enables the user to find the valid data window during operation for each bit of the SPI-4.2 bus. 

- SnkDPAAddrRst (Input): Phase Alignment DPA Ram Address Reset. Active high signal that clears the SnkDPARamAddr counter. 

- SnkDPAAddrEn (Input): Phase Alignment DPA Ram Address Enable. Active high signal that enables the SnkDPARamAddr counter. 

 

For more information, see the SPI-4.2 Core v8.2 User Guide. 

 

Wrapper File Changes 

The v8.2 wrapper file replaces the v8.1 wrapper file. 

 

UCF File Changes 

The UCF file must be updated by replacing all SPI-4.2 constraints in the UCF file with SPI-4.2 constraints provided in the v8.2 release (use the v8.2 UCF files instead of the v8.1 UCF files).

AR# 24014
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article