We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24028

MIG ML461 - Why are the DDR2 SDRAM component clocks terminated with 100 Ohm differential termination between the pair?


The ML461 User Guide (UG079 v1.0) page 45, Table 5-4 indicates that the clock pair (CK, /CK) is using the single-ended SSTL18_II I/O standard. However, the guide also states that the termination at the memory is a 100 Ohm differential termination between the pair. What is the actual termination used on the clock pair and why is this the case?


The CK and /CK pins are used as a differential signal. For Virtex-4, the DIFF_SSTL18_II standard is optimal for this type of signaling. The DIFF_SSTL standards are optimized to minimize the skew between the signal and its complementary inverted pair. Though typical SSTL18_II termination is valid for this type of signaling (source and end termination to VCCO/2 on both P and N sides), using 100 Ohm differential will also properly terminate this link.

AR# 24028
Date 05/20/2014
Status Archive
Type General Article