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AR# 24031

LogiCORE PCI Express v3.2 - Clock correction settings might cause packets to be dropped on asynchronous links

Description

When using an asynchronous link, packets received by the core might appear to get lost or dropped as they never show up at the receiver user interface.

Solution

Under most circumstances, PCI Express links should be synchronously clocked. Asynchronously clocked links should only be used if the designer has full control over the clock oscillators being used on each side of the link. This guarantees that they meet the requirements of the Virtex device being used and that SSC is not being used on either clock source. For more information about synchronous vs. asynchronous PCI Express links, see (Xilinx Answer 19760) and (Xilinx Answer 18329).

Users of asynchronous links need to override the MGT clock correction parameters being used inside the core. This can be done by adding the correct parameters to the UCF file.

With the current v3.2 settings, in the case a symbol has to be added or deleted due to relative clock drifts, the GT11 will incorrectly remove the entire clock correction ordered set (CCOS) (COM, SKP, SKP, SKP). At most, only 1 SKP should be inserted or removed from the stream anytime clock correction is required. Removal of the entire CCOS will cause core de-scrambler to get out of sync with the connected transmitter's scrambler because the COM character that was stripped out is supposed to reset the scrambler/de-scrambler pair.

Users of synchronous links do not need to make this change, but no harm will come if you do. These changes will be added to the v3.4 release of the core, due in December 2006.

Current v3.3 core settings are as follows:

CLK_COR_SEQ_LEN = 4;

CLK_COR_SEQ_1_MASK = 4'b0000;

CLK_COR_SEQ_1_4 = 11'b00100011100;

CLK_COR_SEQ_1_3 = 11'b00100011100;

CLK_COR_SEQ_1_2 = 11'b00100011100;

CLK_COR_SEQ_1_1 = 11'b00110111100;

For each PCI Express lane RocketIO, these should be changed to:

CLK_COR_SEQ_LEN = 1;

CLK_COR_SEQ_1_MASK = 4'b1110;

CLK_COR_SEQ_1_4 = 11'b00000000000;

CLK_COR_SEQ_1_3 = 11'b00000000000;

CLK_COR_SEQ_1_2 = 11'b00000000000;

CLK_COR_SEQ_1_1 = 11'b00100011100;

Following is an example of overriding these for a x1, x4, and x8 link. Please note the paths might vary depending upon the name selected for your core.

x1 Example

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_LEN = 1;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_1_MASK = 4'b1110;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_1_4 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_1_3 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_1_2 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_1_1 = 11'b00100011100;

x4 Example

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_LEN = 1;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_1_MASK = 4'b1110;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_1_4 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_1_3 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_1_2 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_1_1 = 11'b00100011100;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST2" CLK_COR_SEQ_LEN = 1;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST2" CLK_COR_SEQ_1_MASK = 4'b1110;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST2" CLK_COR_SEQ_1_4 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST2" CLK_COR_SEQ_1_3 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST2" CLK_COR_SEQ_1_2 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST2" CLK_COR_SEQ_1_1 = 11'b00100011100;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST3" CLK_COR_SEQ_LEN = 1;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST3" CLK_COR_SEQ_1_MASK = 4'b1110;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST3" CLK_COR_SEQ_1_4 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST3" CLK_COR_SEQ_1_3 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST3" CLK_COR_SEQ_1_2 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST3" CLK_COR_SEQ_1_1 = 11'b00100011100;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST4" CLK_COR_SEQ_LEN = 1;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST4" CLK_COR_SEQ_1_MASK = 4'b1110;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST4" CLK_COR_SEQ_1_4 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST4" CLK_COR_SEQ_1_3 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST4" CLK_COR_SEQ_1_2 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST4" CLK_COR_SEQ_1_1 = 11'b00100011100;

x8 Example

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_LEN = 1;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_1_MASK = 4'b1110;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_1_4 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_1_3 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_1_2 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" CLK_COR_SEQ_1_1 = 11'b00100011100;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST2" CLK_COR_SEQ_LEN = 1;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST2" CLK_COR_SEQ_1_MASK = 4'b1110;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST2" CLK_COR_SEQ_1_4 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST2" CLK_COR_SEQ_1_3 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST2" CLK_COR_SEQ_1_2 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST2" CLK_COR_SEQ_1_1 = 11'b00100011100;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST3" CLK_COR_SEQ_LEN = 1;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST3" CLK_COR_SEQ_1_MASK = 4'b1110;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST3" CLK_COR_SEQ_1_4 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST3" CLK_COR_SEQ_1_3 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST3" CLK_COR_SEQ_1_2 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST3" CLK_COR_SEQ_1_1 = 11'b00100011100;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST4" CLK_COR_SEQ_LEN = 1;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST4" CLK_COR_SEQ_1_MASK = 4'b1110;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST4" CLK_COR_SEQ_1_4 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST4" CLK_COR_SEQ_1_3 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST4" CLK_COR_SEQ_1_2 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST4" CLK_COR_SEQ_1_1 = 11'b00100011100;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST5" CLK_COR_SEQ_LEN = 1;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST5" CLK_COR_SEQ_1_MASK = 4'b1110;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST5" CLK_COR_SEQ_1_4 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST5" CLK_COR_SEQ_1_3 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST5" CLK_COR_SEQ_1_2 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST5" CLK_COR_SEQ_1_1 = 11'b00100011100;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST6" CLK_COR_SEQ_LEN = 1;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST6" CLK_COR_SEQ_1_MASK = 4'b1110;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST6" CLK_COR_SEQ_1_4 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST6" CLK_COR_SEQ_1_3 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST6" CLK_COR_SEQ_1_2 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST6" CLK_COR_SEQ_1_1 = 11'b00100011100;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST7" CLK_COR_SEQ_LEN = 1;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST7" CLK_COR_SEQ_1_MASK = 4'b1110;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST7" CLK_COR_SEQ_1_4 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST7" CLK_COR_SEQ_1_3 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST7" CLK_COR_SEQ_1_2 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST7" CLK_COR_SEQ_1_1 = 11'b00100011100;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST8" CLK_COR_SEQ_LEN = 1;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST8" CLK_COR_SEQ_1_MASK = 4'b1110;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST8" CLK_COR_SEQ_1_4 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST8" CLK_COR_SEQ_1_3 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST8" CLK_COR_SEQ_1_2 = 11'b00000000000;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST8" CLK_COR_SEQ_1_1 = 11'b00100011100;

AR# 24031
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article