In the XCF00P Platform Flash devices, a block table exists that holds pointers to the start of the address space in the device. When an SVF file is generated to erase a single revision of the device, this block table is erased and then re-programmed. This is a redundant step in the programming process as the block table will not change if just the revisions are being operated on.
Problems can occur if the SVF file does not finish playing entirely. If the SVF file fails to finish, this block table can be erased and then not be re-programmed. The PROM will not be able to boot an FPGA from any of the revisions. Erasing this block table will remove all of the pointers to all of the start addresses.
If a reconfiguration is triggered after this SVF file has failed to finish playing, the FPGA will not configure and the PROM will have to be re-programmed.
To avoid this problem, always re-program the PROM and ensure programming files have finished before a reconfiguration is attempted.
This problem should be fixed in the 9.1 release of the Design Environment Tools. The tools will not erase the block table when one revision is erased. At this point, a failure in playing the entire device will not leave the device non-operational.
Note that during configuration of the PROM the device is placed in ISP (In-System Programming) mode. If a programming file (such as an ".ace" or ".svf" file) is not fully played, the device will be left in the ISP state. When the Platform Flash is in ISP mode, only the JTAG pins are active and a configuration cannot be initiated. To get the device out of this mode, there are three options:
- Issue the CONLD command to the device.
- Move the TAP controller of the device to TLR by setting TMS to 1 and clocking TCK 5 times.
- Cycle the power on the PROM.
Any of the above operations will remove the PROM from ISP mode and allow a configuration to be initiated.