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AR# 24071

Virtex-4 DCM - Why does the LOCK output toggle when I hold the DCM in reset?


In a Production Step 2 Virtex-4 device, when the DCM_AUTOCALIBRATION attribute is set to TRUE and the DCM is held in reset, the LOCK signal and, consequently, all DCM outputs toggle. Why does this occur?


In ISE design tool versions 7.1.03i and later, MAP automatically instantiates a clock stop macro for each DCM in a design for the Virtex-4 LX/SX Production Step 2 and higher devices, and Virtex-4 FX ES4 and Production devices. If an active Low reset is used, the LOCK signal toggles when the DCM is held in reset. See (Xilinx Answer 21435) for more information on the clock stop macro.

To work around this issue, change the reset to active High, if possible. If this is not possible, you can work around the issue by manually inserting a LUT configured as an inverter. You will need to place KEEP constraints on the nets into and out of the LUT to prevent the tools from optimizing the LUT away.



assign RESET = ~RESET_N;


LUT1_inst : LUT1
generic map (
INIT => "01") -- Specify LUT to be an inverter
port map (
O => RESET, -- Output of LUT, route to reset port of DCM
I0 => RESET_N -- Active low reset input to LUT

The following constraints must be added to the ".ucf" file;

NET "RESET_N_IBUF" KEEP; #The net coming from the active low reset pad needs to be constrained, check in FPGA Editor for the correct name of the net

NOTE: If you are using Synplify, you must apply the synthesis syn_keep = 1 constraint to the nets in HDL as well as to the ".ucf" file.
AR# 24071
Date 12/15/2012
Status Active
Type General Article
  • Virtex-4 FX
  • Virtex-4 LX
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