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AR# 24102

8.2i EDK SP2 - fsl_v20_v2_00_a: in the core data sheet, the description for C_FSL_DEPTH is incorrect

Description

The fsl_v20_v2_00_a documentation includes the following on page four: 

 

"C_FSL_DEPTH 

Specifies the depth of the FIFO implemented by the FSL bus. The depth can be as low as 1 or as high as 8192. The depth that can be specified is dependent on the implementation scheme of the FIFO. When the parameter C_ASYNC_CLKS is set to 0, the maximum depth allowed is 128. When the parameter C_ASYNC_CLKS is set to 1, the maximum allowable depth is 8192." 

 

This description is confusing because it does not match what is in the MPD file for this core: 

 

"PARAMETER C_FSL_DEPTH = 16, DT = integer, RANGE = (0:C_ASYNC_CLKS*128 | !C_ASYNC_CLKS*8192)" 

 

Is the MPD file or the documentation correct?

Solution

The documentation is incorrect; it should state the following: 

 

"C_FSL_DEPTH 

Specifies the depth of the FIFO implemented by the FSL bus. The depth can be as low as 1 or as high as 8192. The depth that can be specified is dependent on the implementation scheme of the FIFO. When the parameter C_ASYNC_CLKS is set to 0, the maximum depth allowed is 8192. When the parameter C_ASYNC_CLKS is set to 1, the maximum allowable depth is 128." 

 

That is, when in synchronous mode, the depth can be 8192 and not 128 and in asynchronous mode it can only be 128. 

 

This description matches the MPD file for this core: 

 

"PARAMETER C_FSL_DEPTH = 16, DT = integer, RANGE = (0:C_ASYNC_CLKS*128 | !C_ASYNC_CLKS*8192)" 

 

This issue has been corrected in the documentation for fsl_v20_v2_10_a, which will be released in EDK 9.1i, scheduled for 2007.

AR# 24102
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article