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AR# 24108: 9.1i, Incremental Design Flow - Incremental Design for Reuse in ISE 9.1i
9.1i, Incremental Design Flow - Incremental Design for Reuse in ISE 9.1i
What is the migration for old Incremental Design Flow to the new Partition-based Incremental Design Flow?
This Answer Record describes the process of new incremental design for reuse in ISE 8.2i. It also discusses the previous incremental design for reuse in 8.1i and older. The new incremental design for reuse is done through Partitions, and the creation of Partitions is described.
Old Incremental Design for Reuse (Prior to ISE 8.2i)
Prior to ISE 8.2i, you had to inform XST concerning which modules needed to be updated. Then, XST would re-synthesize only those modules. This was done via the MODEL, and INCREMENTAL_SYNTHESIS constraints in the XCF file or HDL file. The INCREMENTAL_SYNTHESIS was to control which modules were preserved or re-synthesized.
Each module that was labeled as INCREMENTAL_SYNTHESIS had to be constrained via an AREA_GROUP constraint and RANGE constraint. Once all necessary modules were constrained, you also had to specify the "-gm incremental" and "-gf <guide_file.ncd>" switches in MAP and PAR. This caused MAP and PAR to compare the previous NCD (guide_file.ncd) to the current design file and determine which portions needed to be re-implemented.
New Incremental Design for Reuse
In ISE 8.2i, XST no longer requires the use of the synthesis constraints, so the physical constraints should be removed. Please remove the MODEL and INCREMENTAL_SYNTHESIS constraints from the XCF and remove the rangeless AREA_GROUP constraints from the UCF. The "-gm" and "-gf" switches for MAP and PAR are no longer required. Instead, Project Navigator will automatically identify which modules have been updated and XST will re-synthesize only those modules/instances that have a Partition. Partitions enable design reuse and can help reduce run-time of implementation.
Create a Partition on the same modules or instances that had the MODEL and INCREMENTAL_SYNTHESIS constraints. Do not create a Partition for the top level of the design, as it is already done for you by Project Navigator. This can be done in Project Navigator or via Tcl. In Project Navigator, right-mouse-click the module or instance and select "New Partition" from the popup menu. In Tcl, type the following either in script, xtclsh, or Tcl console: "partition new <instance_name>" or "partition new /dve_ccir_top/GENERATOR". More information can be found in the ISE Help, under Reaching Design Closure for FPGA.
Figure 1 - New Partition Dialog in Project Navigator
Partitions can be created on any instance in your logical design to indicate that the implementation for that instance should be reused when possible. Partitions can nest hierarchically and be defined on any HDL module instance in the design. A module with multiple instances can have multiple Partitions - a Partition for each instance. Partitions should be placed on the wrappers of IP cores, but not the cores themselves. The top level of the HDL design defaults to a Partition.
Partitions can contain logic at the top level of the design and do not require ranges or AREA_GROUP constraints. A Partition defines a source instance that is marked for reuse and can be HDL, Schematic, or Edif source instances at any level of the hierarchy. When a lower-level source instance is defined as a Partition, the top module is automatically defined as a Partition as well. Partitions are enabled by creating a Partition for a node in the design hierarchy. In Verilog, the Partition is set on a module instance; in VHDL, the Partition is set on an entity architecture.
Partitions will be re-implemented after a command line change, constraint change, or implementation option change. Partitions automatically detect input source changes, which include HDL changes and certain changes in the constraint files such as physical constraints and location constraint ranges on Partitions in the UCF. If a command line option changes, such as effort levels on the implementation tools, only the affected Partitions are reimplemented.
The Area Constraints or AREA Groups that were associated with the incremental design modules can now be associated with Partitions. As the new Partition allows the use of AREA Group constraints, you will be able to create Partitions for the user-defined hierarchical area groups and keep the existing AREA Group constraints with the corresponding implementation options (RANGE, COMPRESSION, PLACE, etc.). The AREA constraints must be created with the INST syntax in the UCF file.
In addition to Project Navigator knowing when a module has been updated, it also uses the previously implemented design run to copy and paste portions of the design that have not been updated. This means that the implementation tools will reuse the previous design implementation on the current design interaction. This helps to decrease runtime and memory usage.
To use Partitions most efficiently, place the registers that drive, or are driven by I/O, at the top level of the design. Place the ODDR and IDDR at the top level of the design. Also, place registers at the input and output of the partition module. The Partition must be placed on the instance or module prior to synthesis and implementation. This allows the implementation tools to know which modules or instances might need to be reused or reimplemented in the next interaction of the design.
Recommendation for Incremental Design for Reuse
It is recommended that Partitions be placed on major or timing-critical modules. This allows the synthesis and implementation tools to use the previous version of the design for reuse and synthesize and implement the change partition. This will help to reduce runtime and the memory usage of the implementation tools. The creation of Partitions can be done through Project Navigator or the Tcl interface.
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