AR# 24112


8.2.01 System Generator for DSP - Release Notes/README and Known Issues List


This Answer Record contains the Release Notes and Known Issues for System Generator for DSP 8.2.01.


For System Generator for DSP release notes from other release versions, see (Xilinx Answer 29595).

Known Issues in System Generator for DSP 8.2.01

System Generator for DSP 8.2.01 is a minor update, and is highly recommended for all System Generator for DSP 8.2 users. Please read the documentation, as it answers questions about changes in the functionality from previous versions of System Generator for DSP. The System Generator User Guide PDF Version is accessible from:

Support Software Issues

- What software do I need to install System Generator for DSP? See (Xilinx Answer 17966).

- XST bus elaboration might cause interface changes. See (Xilinx Answer 18650).

- Why is my old System Generator for DSP missing, or seems to have disappeared when running xlVersion after installing 8.1? See (Xilinx Answer 22756).

- How do I enable Virtex-5 LXT support? See (Xilinx Answer 24158).

NOTE: The Hardware in the Loop Ethernet Co-Simulation System ACE file was updated in System Generator for DSP 8.1.01. You should rerun the CF card update utility to ensure that you have the latest version installed on your System ACE Compact Flash Card.

Xilinx Blockset Issues

- Why do I see simulation mismatches with the DDS v4.0 when both the reset port and pipelining are enabled? See (Xilinx Answer 22709).

- PicoBlaze compiler script fails when using long module names. See (Xilinx Answer 16924).

- Why does XST "Error 1370 ..." occur when using Verilog as my target language with a DDS v4.0 or v5.0 in my design? See (Xilinx Answer 22713).

- Simulation mismatched for the reloadable DA FIR when performing back-annotated simulation. See (Xilinx Answer 19505).

- Why does my System Generator for DSP 6.3 or 7.1 design (which passed generics to the black box for port widths) fail in System Generator for DSP 8.1 or greater? See (Xilinx Answer 22715).

- Why are my Gateway In blocks behaving differently between System Generator for DSP 7.1, 8.1 and 8.1.01 and greater? See (Xilinx Answer 23250).

- Why do I see the following error, "Internal Block Error: This block set an illegal type on its "gw_out_inport" port. The type setting was illegal because Unknown type"? See (Xilinx Answer 23252).

- Why does my design fail to generate when using a FIFO block, From FIFO block, or To FIFO block in my design, and my target path is more than 160 characters? See (Xilinx Answer 23614).

- Why do designs with more than 256 characters in the path fail to synthesize in XST? See (Xilinx Answer 23811).

- Why do I receive errors when trying to implement the FFT v1.0 with Synplify Pro? See (Xilinx Answer 23813).

- Why do I receive an error when the "Specify explicit sample period" option is selected and the "Provide enable port" or "Provide synchronous reset port" are not selected, on my Direct Digital Synthesis (DDS) v5.0 block? See (Xilinx Answer 23814).

- Why do I receive an "NGDBUILD:76" error reporting that the addra address pins are not being found, when I have a shared memory block in my design that has only two locations? See (Xilinx Answer 24266).

- Why are the clock pin LOC constraints being ignored when I netlist using the Multiple Subsystem Generator (MSG) block? See (Xilinx Answer 24270).

- Why are shared memories removed from my design during generation? See (Xilinx Answer 24271).

- Why are there simulation mismatches when there are two different data types on the two data inputs of my Dual Port Block RAM (DPRAM) block? See (Xilinx Answer 24272).

- Why do the outputs of my FROM and TO registers appear to be incorrect when I use the Free Running Clock with Hardware in the Loop (HITL) Co-Simulation? See (Xilinx Answer 23206).

- When can I use the Shared Memory, Shared Memory Read, Shared Memory Write , FROM and TO FIFO, and FROM and TO Registers in my design? See (Xilinx Answer 24290).

- Why do I get a time out error when using the Shared Memory or Shared FIFO blocks in my design? See (Xilinx Answer 24288).

General Issues

- The following error is reported during generation: "Undefined function or variable." See (Xilinx Answer 15190).

- Generation fails when the Simulation Stop Function is defined for a model. See (Xilinx Answer 18623).

- User Hardware Co-Sim files disappear when installing System Generator for DSP update. See (Xilinx Answer 18646).

- JTAG Hardware Co-Sim with non-Xilinx parts in the chain causes error. See (Xilinx Answer 19599).

- How can I improve the synthesis results of the clock wrapper clock enable logic? See (Xilinx Answer 23253).

- Why do designs with more than 256 characters in the path fail to synthesize in XST? See (Xilinx Answer 23811).

- Why does System Generator for DSP hang when generating my large Verilog design? See (Xilinx Answer 20962).

- Why do I receive "Error evaluating 'OpenFcn' callback of Xilinx Block. Error using ==> xlOpenGui" Cannot parse XLM file when I try to open a SysGen block on a network installation, or after installing a new version. See (Xilinx Answer 23223).

- How can I change the implementation options for the Timing Analysis flow? See (Xilinx Answer 24263).

- Why is the output type on the Gateway Out different than expected, and why does the output data appear incorrect when viewing it with a Simulink Scope? See (Xilinx Answer 23265).

- Why do I get "Error 0001: caught standard exception" error" when using IBM Clear Case? See (Xilinx Answer 24263).

- Why do post-PAR simulation mismatches occur when running a design at faster than 200 MHz? See (Xilinx Answer 24268).

- I cannot generate an NGC, Bitstream, Timing Analysis, or Hardware in the Loop target when using Synplify as my synthesis tool. Why? See (Xilinx Answer 24273).

- Why do I see an instantiated register called "xlpersistentdff" in my System Generator for DSP design? See (Xilinx Answer 24257)

AR# 24112
Date 12/15/2012
Status Active
Type General Article
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