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AR# 24123

8.2i EDK - An ML501 board design that uses an MCH_OPB_DDR2 Core does not work

Description

The built-in memory test fails in a Base System Builder (BSB) generated ML501 design that uses the OPB_DDR2.

Solution

The BSB constructs the clocking stream inefficiently, which causes skew between the two DCMs. To resolve this issue, replace the following lines in the MHS file with the new information below: 

 

Replace: 

 

BEGIN mch_opb_ddr2 

PARAMETER INSTANCE = DDR2_SDRAM_32Mx32 

PORT Device_Clk = clk_200mhz_s  

END 

 

BEGIN util_vector_logic 

PARAMETER INSTANCE = ddr2_devclk_inv 

PORT Op1 = clk_200mhz_s  

END 

 

BEGIN dcm_module 

PARAMETER INSTANCE = dcm_1 

PORT CLK0 = dcm_1_FB 

PORT CLKFB = dcm_1_FB  

END 

 

 

With: 

 

BEGIN mch_opb_ddr2 

PARAMETER INSTANCE = DDR2_SDRAM_32Mx32 

PORT Device_Clk = ddr2_dev_clk_s  

END 

 

BEGIN util_vector_logic 

PARAMETER INSTANCE = ddr2_devclk_inv 

PORT Op1 = ddr2_dev_clk_s  

END 

 

BEGIN dcm_module 

PARAMETER INSTANCE = dcm_1 

PORT CLK0 = ddr2_dev_clk_s 

PORT CLKFB = ddr2_dev_clk_s  

END 

 

 

The above changes use the same DCM connection for the Device_clk and Device_Clk90_in; this eliminates the skew caused by having these clock pins come from separate DCMs.

AR# 24123
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article