In Virtex-5 LXT ES silicon, the transmit signals between the fabric and GTP must be registered and locked down to meet timing. The example design rocketio_wrapper.v/vhd for v7.0 provides LOC constraints for a 5VLX50T GTP_DUAL_X0Y0 and GTP_DUAL_X0Y1. These registers and LOC constraints are not in the example design for v7.1, as this is no longer required for production devices. If a different device or GTP location is used with v7.0, or if ES silicon is used with v7.1, follow the instructions below to generate the correct constraints with the RocketIO GTP Wizard.
You can use the RocketIO GTP Wizard to generate a new rocketio_wrapper.v/.vhd with the LOC constraints for a different device and GTP locations. Use the following steps to replace the original rocketio_wrapper.v/vhd in the XAUI core example_design directory:
1. Run the RocketIO GTP Wizard in CORE Generator with the correct target device. Leave all of the options as the default, except:
- On page 1, choose the GTPs that will be used. The component name must be rocketio_wrapper, which is the default.
- On page 2 of the RocketIO GTP Wizard, select the following:
targetline rate: 3.125 Gbps
Check the "Use Dynamic Reconfiguration Port" box
GTP0 protocol template: xaui
GTP1 protocol template: use GTP0 settings
- On page 6 of the Rocket IO GTP Wizard, if the core is not using the IEEE statemachines, select the following:
(If the core is using the IEEE Statemachines, no change is required)
Under RXLOSSOFSYNCPortMeaning, select: Loss-of-Sync State Machine status
2. The output will contain the constraints embedded into the GTP wrapper code in <coregen_project>/<core_name>/src/rocketio_wrapper.v/vhd. Copy this file into the XAUI core example_design directory.
3. If using Solaris/Linux, you must edit the rocketio_wrapper.v/vhd file to change the occurrences of ROCKETIO_WRAPPER and ROCKETIO_WRAPPER_TILE from uppercase to lowercase. You can edit the file in a text editor with the Find and Replace function.