UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24185

11.1 Incremental Design/Partition/Project Navigator - When should I use partitions?

Description

Keywords: do, don't, do not

When should I use partitions?

Solution

Use Partitions

Use partitions when:
- You want 100% preservation on a hierarchical block.
- You want to lock down a hierarchical block in the design.
- Your design has major functional blocks that are broken up by natural design hierarchy (e.g., large designs, team-based designs, EDK designs, DSP designs).
- Your design has "whack-a-mole" timing problems.
- You want to receive resource utilization statistics per hierarchical block.
- You cannot use SmartGuide (e.g., it uses too much memory; you do not want map-timing; you are making design changes that result in major changes in synthesis results).
- You want to use Partial Reconfig or Team Design (future).
- You want to improve implementation runtime (and turns per day). Note that SmartGuide also improves implementation runtimes.
- You want to improve synthesis runtimes (and turns per day). Note that SmartGuide does not improve synthesis runtimes.
- You are making "large" changes to the design. If the design is highly utilized, this might require backing off preservation levels of unchanged partitions.
- You want a finer level of control over preservation. Note that SmartGuide is either on or off and applies to the whole design. Partitions support per-partition preservation control of synthesis, placement, or routing.

Do Not Use Partitions

Do not use partitions when:
- You want global optimization across all hierarchical blocks.
- Your flat design is not meeting timing and you do not have hierarchical blocks that can be partitioned without further damaging the timing.
- Your flat design has high slice utilization.
- You have "ifdefs" in your source code.
- You have VHDL Libraries.
- You have "include" files in a local directory or explicit path.
- Your synthesis tool comes from Mentor.
- Your synthesis tool is basic Synplify (without support for compile points).
- Your TBUF is crossing Partitions.
- You have I/O DDR, I/O, or I/O Register is a lower-level module.
- Your synthesis tool in ISE is Simplicity; must use standalone.
- You cannot do bottom up synthesis flow.
- You cannot use on Generate Statement instances for HDL designs.
- You cannot use on cores; must place them on a wrapper.
- You cannot use the EDK flow; must use a wrapper.
- Your critical path is between partitioned modules.
- Your timing margins are very small.
- You have active low control signals in Virtex-5 devices.
- If hierarchical blocks are in the same file and change one block, all the partitions are reimplemented.

If you cannot use partitions, use SmartGuide to reduce runtime and improve efficiency.
AR# 24185
Date Created 09/04/2007
Last Updated 06/25/2009
Status Active
Type General Article