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AR# 24216

8.2i EDK SP2 mch_opb_ddr2_v1_01_a: Implementing mch_opb_ddr2 controller with EDK 8.2i SP2 results in timing error

Description

I created my design with Base System Builder, and implemented it with mch_opb_ddr2 in EDK 8.2i SP2.The tool reports that the timing is not met:

"Slack: -1.570ns (requirement - (data path - clock path skew + uncertainty))

Source: mb_opb/mb_opb/POR_FF_I (FF)

Destination: ddr2_sdram_32mx64/ddr2_sdram_32mx64/WO_ECC.DDR_CTRL_I/WO_ECC.IO_REG_I/VIRTEX4_IOREGS.DDR_D

Q_REG_GEN[41].DDR_DQ_REG_V4_I (FF)

Requirement: 2.500ns

Data Path Delay: 2.743ns (Levels of Logic = 0)

Clock Path Skew: -1.092ns

............................

..........................."

Solution

To work around this issue, add the following constraints to the UCF file:

NET "mb_opb_OPB_Rst" TIG;

Net "dlmb_port_BRAM_Clk" TNM = "TN_BRAM_CLK";

Net "clk_200mhz_s" TNM = "TN_clk_200mhz_s";

TIMESPEC "TS_BRAMCLK2clk_200mhz_s" = FROM "TN_BRAM_CLK" TO "TN_clk_200mhz_s" TIG;

TIMESPEC "TS_clk_200mhz2BRAMCLK" = FROM "TN_clk_200mhz_s" TO "TN_BRAM_CLK" TIG;

This issue will be fixed in a future release of the tool.

AR# 24216
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article