We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24220

Timing - Clock skew master record


Where can I find information about clock skew?


The Timing tool supports a path delay analysis that accounts for clock skew.

The clock skew is added to the calculated data path delay to arrive at a total path delay that is compared to the constraint (or reported as the delay for the path when the constraint has no value).  
Note: Skew is taken into account only when it works against the constraint and is truncated to zero if the reverse is true. 
How does clock skew affect setup/hold analysis? See (Xilinx Answer 17224)
How is clock skew calculated? See (Xilinx Answer 39744)
Information on large clock skew on global buffer? See (Xilinx Answer 15807)
Information on clock skew difference in PAR table compared to the timing report? See (Xilinx Answer 14578)
Information on clock skew affected by external feedback on DCM? See (Xilinx Answer 15621)
Information on truncated clock skew to zero? See (Xilinx Answer 23936)
How Clock Skew affects Hold/Race Checks See (Xilinx Answer 24289).
AR# 24220
Date 09/04/2014
Status Active
Type General Article
  • ISE Design Suite
Page Bookmarked