This Release Note is for the Block Memory Generator Core v2.3 released in 8.2i IP Update 3 and contains the following information:
- New Features
- Bug Fixes
- Known Issues
For installation instructions and design tools requirements, see (Xilinx Answer 24226).
The Xilinx Block Memory Generator v2.3 LogiCORE should be used in all new Virtex-5, Virtex-4, Virtex-II, Virtex-II Pro, Spartan-II/-E, Spartan-3E, and Spartan-3 designs wherever block memory is required. This core supersedes the Single Port Block Memory v6.2 and Dual Port Block Memory v6.3 cores, but is not a direct drop-in replacement. See the Block Memory Core Migration Kit available at:
New Features in v2.3
- None at this time
Bug Fixes in v2.3
(Xilinx Answer 24104) When using Byte Write Enable feature, the data read-out from the memory might not match what is expected.
(Xilinx Answer 24061) Unexpected data is seen on the output as the memory is generated with the incorrect write mode.
(Xilinx Answer 24069) Memory is not initialized correctly using the COE or "Filling Memory Locations" option.
(Xilinx Answer 24033) Block Memory Resource Estimate (on last page of GUI) reports "undefined".
(Xilinx Answer 24057) Spartan-3A is a supported device, although the table on page one of the data sheet "Supported Device Family" does not mention that this device is supported.
Known Issues in v2.3
(Xilinx Answer 23688) Block Memory Generator GUI will not open on Linux and Solaris when project directory is in "$XILINX".
(Xilinx Answer 23744) Invalid address input can cause the core to generate Xs on the DOUT bus.
(Xilinx Answer 24034) Block Memory Generator Core takes a long time to generate.
(Xilinx Answer 24313) The core might issue unexpected outputs and simulation warning: "# ** Warning: Functional warning at simulation time ..."
The Virtex-5 Errata is located at:
The Block Memory Generator Core is subject to all block RAM issues listed in the Errata.