Why do post-PAR simulation mismatches occur when I run the design faster than 200 MHz?
In most cases, the behavioral simulation is correct, but because of delay introduced by the IOBs, the post-PAR simulation outputs are delayed and do not align with the golden results produced in MATLAB. This functionality should not be a problem if a fast I/O Standard is selected.
In some cases, this issue can be problematic with behavioral simulation resulting from a delay in the simulation model for some cores. If you perform a post-translate simulation, this should not be a problem.
For some blocks, you can also switch off the core generation and use behavioral code. This solution can yield better performance and does not have the behavioral simulation mismatches.