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AR# 24282

8.2i Simprim - Output of Verilog Simprim model IODELAY is incorrect


Output of Verilog Simprim model IODELAY is incorrect, which causes SPI-4.2 core to fail.


Please open a WebCase with Xilinx Technical Support at: http://www.xilinx.com/support/clearexpress/websupport.htm to receive a solution for this issue.  


This issue is fixed in ISE 9.1i

AR# 24282
Date 05/20/2014
Status Archive
Type General Article
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