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AR# 24283

8.2i Sp3 Simprims - Virtex-5 Output DOB of Verilog model of X_RAMB36_EXP is incorrect


During the Verilog timing simulation for the SPI-4.2 Core design, the output DOB of X_RAMB36_EXP is incorrect


Please open a WebCase with Xilinx Technical Support at: http://www.xilinx.com/support/clearexpress/websupport.htmto receive a solution for this issue.

This issue is fixed in ISE 9.1i

AR# 24283
Date 12/15/2012
Status Active
Type General Article
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