For Virtex-5 LXT Verilog SGMII designs, a typo must be corrected in the "<component_name>_block.v" example design wrapper file. This is not a problem if using VHDL.
The file "<component_name>_block.v" can be found in the "<component_name>\example_design" directory.
This is the current code in the instantiation of the "sgmii_adapt" module:
This should be changed to:
That is, remove the "_reg".
This will be fixed in version 8.1 of the core scheduled to be released in 9.1i IPUpdate1, which is scheduled to be out in February 2007.