When simulating Serial Rapid IO core, memory collision error similar to following can be seen:
# Memory Collision Error on RAMB16_S36_S36:ep_tb.ep_sim.buffer_sim.tx_wrapper.tx_channel_fifo.ramb0_31_0.display_wa_rb at simulation time 3291.200 ns
# A read was performed on address 000 (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.
# Memory Collision Error on RAMB16_S36_S36:ep_tb.ep_sim.buffer_sim.tx_wrapper.tx_channel_fifo.ramb0_63_32.display_wa_rb at simulation time 3291.200 ns
# A read was performed on address 000 (hex) of Port B while a write was requested to the same address on Port A. The write will be successful; however, the read value on Port B is unknown until the next CLKB cycle.
Within the SRIO Core, the memory is being read while it is empty; then, when the first packet information is written into the FIFO, the read and write are performed in the same cycle. The core is written this way for latency optimization. We want to start operating on the first packet as soon as it is available; therefore, we continue to read an empty memory. The contents of the memory define its functionality, which is why this does not hurt. The memory is defined so that old data is read out in this particular cycle, but when we read again the next cycle, we get the data written at the time of the warning, including a field indicating its validity.
These memory collision errors can be ignored if they are coming from Serial Rapid IO core.