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AR# 24420

8.2i EDK - Clock frequency value in an XBD file is rounded

Description

The following module is defined in XBD: 

 

BEGIN IO_INTERFACE 

ATTRIBUTE INSTANCE = clk_1 

ATTRIBUTE IOTYPE = XIL_CLOCK_V1 

PARAMETER CLK_FREQ = 3686400, IO_IS = clk_freq 

END 

 

This module is converted to the following in the MHS file after creating new project using the wizard: 

 

PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 3690000 

 

CLK_FREQ is converted from 3686400 to 3690000.

Solution

To work around this issue, you should manually edit the MHS file. This issue will be fixed in EDK 9.1i, scheduled for 2007.

AR# 24420
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article