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AR# 24432

MIG v2.0 - How can I map the address for the DDR2 SDRAM user interface to account for auto-precharge bit A10?

Description

For MIG-generated Virtex-4 DDR/DDR2 SDRAM designs, the address bus AF_ADDR, read by the controller to generate the memory interface address bus is made discontinuous by the auto-precharge bit A10. You must account for this discontinuity when driving the backend address APP_AF_ADDR by skipping, or tying Low, bit A10 and potentially bit A9.

Solution

This information is now available in the MIG User Guide.

When a memory device receives a column access, bit 10 (A10) is read to determine if an auto-precharge occurs at the end of the burst. MIG designs do not support auto-precharge, but reserve bit A10 for users wanting to implement custom auto-precharge logic. If this custom logic is not implemented, A10 needs to be set to "0" to disable auto-precharge.

Starting with MIG v1.6, the DDR/DDR2 SDRAM controller ignores bit 10 of the address sent by the user backend and forces A10 to zero on a column access. Consequently, you can either skip over this bit or tie it to "0." MIG controllers released prior to MIG version 1.6 do not force bit A10 to "0". As a result, you MUST tie bit 10 of the address to "0." If A10 was set to one, the memory device would expect an auto-precharge that the MIG controller does not send.

Based on the number of column bits, you must drive the user backend address bus APP_AF_ADDR differently to account for the auto-precharge bit A10. When interfacing to DDR/DDR2 devices with 10 or more columns bits, AF_ADDR [10] is ignored by the controller logic. When interfacing to DDR/DDR2 devices with only nine column bits (DDR - 128 Mb x16 or 256 Mb x16 wide, DDR2 - 256 Mbit x16 wide), AF_ADDR[10:9] are ignored. You must be aware of these unused bit(s) and drive the user backend address bus APP_AF_ADDR appropriately.

An example of ignoring only AF_ADDR[10] is a DDR2 bus interfacing to a single Micron MT47V32M16 (512Mbit, x16 wide) device. Here, the address bus accesses 2^25 word locations (10 column + 13 row + 2 bank = 25 bits). The user backend address APP_AF_ADDR should be driven as shown below, skipping bit AF_ADDR[10] or tying Low:

APP_AF_ADDR[9:0] = COLUMN_ADDR[9:0]

APP_AF_ADDR[10] = 0 / *unused, tie off */

APP_AF_ADDR[23:11] = ROW_ADDR[12:0]

APP_AF_ADDR[25:24] = BANK_ADDR[1:0]

An example of ignoring AF_ADDR[10:9] is a DDR2 bus interfacing to a single Micron MT47V16M16 (256 Mbit, x16 wide) device. In this example, the address bus accesses 2^24 word locations (9 column + 13 row + 2 bank = 24 bits). The user backend address APP_AF_ADDR should be driven as shown below, skipping bits AF_ADDR[10:9]:

APP_AF_ADDR[8:0] = COLUMN_ADDR[8:0]

APP_AF_ADDR[10:9] = 0 / *unused, tie two bits off */

APP_AF_ADDR[23:11] = ROW_ADDR[12:0]

APP_AF_ADDR[25:24] = BANK_ADDR[1:0]

NOTE: For Virtex-5 DDR/DDR2, starting with MIG v1.7, you are no longer required to always set address A10 (and skip this bit in the memory space) when issuing a command to the controller to prevent an auto-precharge from occurring on the DDR/DDR2 bus. The controller now always forces this bit to "0" on the DDR2 bus, and the memory space presented to you is now linear.

AR# 24432
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 SX
IP
  • MIG