My design has a pad with an OSERDES on the output side with a GND'd REV pin. The input side has an IDDR with a GND'd S pin that should end on the REV pin except that it is being optimized away; this causes the following DRC error at BitGen:
"WARNING:PhysDesignRules:1019 - The placed OSERDES component OSERDES_inst has the
REV pin connected to the signal GLOBAL_LOGIC0 while the adjacent site has the
placed ILOGIC component Q1_OBUF with the REV pin unconnected. This is a
resource conflict since the unconnected pin cannot be tied off as part of
bitstream generation. Both pins should either be connected to the same signal
or they should both be left unconnected."
Ideally, MAP should maintain consistency in control pin usage and not perform this optimization. What can I do to work around this problem?
MAP is supposed to maintain consistency in the control pin usage for the ILOGIC/OLOGIC pairs because the control pins share a routing resource. A fix for this issue is planned for ISE version 9.1i SP2, which is scheduled for February, 2007.
Meanwhile, you can avoid this problem by making the following changes:
- Instantiate a LUT1 inverter
- LUT1 is driven by VCC
- LUT1 drives REV pin of OSERDES and S pin of IDDR
- LOCK_PINS constraint on LUT1 prevents optimization