We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24434

9.1i Tcl - Some process properties are not accessed correctly with Tcl commands "project set" and "project get"


Keywords: xtclsh, MAP, PAR, extra, effort, register, duplication, directories, compile, list, file, IOBs, removal, equivalent, optimization, hierarchy

Some process properties are not accessed correctly with Tcl commands "project set" and "project get."


The project get "register duplication" command does not work for the MAP process property "register duplication." The Tcl command: project get "register duplication," or project set "register duplication" true only returns or modifies the "Register Duplication" option of XST.


In ISE 9.1i, the "project get" and "project set" commands find the first occurrences of a property name if the complete command is not entered. In the example above, you should specify the MAP process to obtain the "register duplication" value for the MAP process as follows:

project set "Register Duplication" true -process map
project get "Register Duplication" -process map

Where there is a possibility for ambiguity, it is a good idea to always specify the process intended. In a future release, these commands will trap ambiguous commands and issue a warning explaining the possible processes for which the property could apply.

A list of identical and similarly named properties for processes follows:

XST: Optimization Effort
MAP: Effort Level

XST: Keep Hierarchy
NetGen: Retain Hierarchy

XST: Global Optimization Goal
MAP: Global Optimization

XST: Register Duplication
MAP: Register Duplication

XST: Add I/O Buffers
NGDBuild: Create I/O Pads from Ports

XST: Equivalent Register Removal
MAP: Equivalent Register Removal

XST: Register Balancing
MAP: Retiming

XST: Pack I/O Registers into IOBs
MAP: Pack I/O Registers/Latches into IOBs

ISim: Custom Compile File List
XST: Custom Compile File List

XST: Verilog Include Directories
ISim: Specify Search Directories for -include

MAP: Extra Effort
PAR: Extra Effort (Highest PAR level only)
AR# 24434
Date 04/17/2009
Status Archive
Type General Article