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AR# 24435

9.1i IP Update 1 and 9.1i IP Update 2 CORE Generator IP-DSP - What's New and Known Issues List

Description

This Answer Record for the CORE Generator contains the IP-DSP What's New and Known Issues addressed in the 9.1i IP Update 2 and 9.1i Update 3, and contains the following:

- New Features

- Bug Fixes

- Known Issues

For installation instructions and design tools requirements, see (Xilinx Answer 24226).

Solution

What's New in 9.1i IP Update 2

IP Update 2 adds support for the Spartan-3A DSP devices to all the cores listed below in 9.1i IP Update 1.

What's New in 9.1i IP Update 1

LogiCORE Fast Fourier Transform (xFFT) v4.1

The Fast Fourier Transform LogiCORE offers a wide range of configurations that allow you to make tradeoffs between high throughput configurations requiring higher resource utilization, and more economical lower throughput implementations with correspondingly lower resource requirements.

New Features in v4.1

- None

Bug Fixes in v4.1

- CR430617: Radix-2-Lite architecture data mismatch when BFP used

- CR430722: Output data mismatch when using 52x18 complex multiplier configuration

- CR430131: Timing diagrams for Burst-I/O solutions with natural-order output are misleading

- CR430302: FFT v4.0 data sheet has some incorrect performance and resource utilization data

- CR429986: Minor errors in data sheet diagrams

- CR429769: Exception reported when generating core

LogiCORE FIR Compiler v3.0

New Features in v3.0

- Support added for ISE 9.1i.

- Maximum number of channels increased to 64.

- Maximum number of coefficient sets increased to 256.

- Supports reloading of multiple coefficient sets.

- Maximum integer rate change increased to 64.

- Fractional rate changes up to 64/63 now supported.

- Exploits symmetry when interpolating by an even rate with an odd number of coefficients, reducing resource utilization.

Bug Fixes in v3.0

- CR 424680: Failure to generate a decimating halfband filter

- CR 426435: Inter-column pipeline uses SRL16s

LogiCORE Multiplier Generator v10.0

New Features in v10.0

- None

Bug Fixes in v10.0

- CR416215: Optimum latency incorrect for Virtex-2, Spartan-3, Spartan-3E symmetric hybrids

- CR416222: DSP48-based multipliers could use fewer slices

- CR416229: CCM generates incorrect VHDL for B=2^64-1

- CR416277: Exception in non-debug model for Multiplier v9.0

- CR416315: CCMs with all-ones as the constant fail to generate

- CR419960: LUT mults with odd operand widths have reduced performance

- CR427806: LUT/FF resource figure missing from data sheet for Virtex-5 18x18 multiplier

- CR433300: Multiplier Generator v9.0 - Does not use DSP48 slices

LogiCORE Turbo Decoder 3GPP2 v2.1

New Features in v2.1

- Support added for Virtex-4 and Virtex-5 devices.

- Support added for cdma2000 High Rate Packet Data Air Interface Specifications, "3GPP2 C.S0024-B V1.0" and "3GPP2 C.S0024-A V2.0".

- ISE 9.1i support.

- Increased dynamic range supported with a 2-bit increase in the supported input integer and internal metric integer bit widths.

Bug Fixes in v2.1

- None

LogiCORE Turbo Encoder 3GPP2 v2.0

New Features in v2.0

- Implements block sizes specified by 3GPP2 C.S0024-B .

Bug Fixes in v2.0

- None

LogiCORE Turbo Encoder (CTC) 802.16e v2.1

New Features in v2.1

- None

Bug Fixes in v2.0

- CR 232447: Incorrect switching of alternate data couples.

-- Symptom: Incorrect data on PAR_Y2 and PAR_W2 outputs. The core was changed to comply with amendment Cor1/D5 of IEEE P802.16, which specifies switching of alternate data couples on ODD interleaver addresses.

- CR 234370: Incorrect timing of RFFD output.

-- Symptom: If FD_IN is sampled high on the first active clock edge after the core asserts RFFD, there will be errors in PAR_Y2 and PAR_W2 outputs, and errors in the last bit of either or both systematic outputs. This occurs because the core asserts RFFD one clock too early.

Bug Fixes in v2.1

The following bug fixes delivered in v2.0 rev1 have been rolled into this release:

- CR 427689 - Hardware timeout associated with evaluation mode is enabled even if a full license exists.

Known Issues in 9.1i IP Update 1

LogiCORE Fast Fourier Transform (xFFT) v4.1

- Why does FIR Compiler, Floating Point Operator, and Fast Fourier Transform error out when attempting to customize them on Solaris? See (Xilinx Answer 24317).

- Why does the Fast Fourier Transform Core take so long to generate? See (Xilinx Answer 24318).

- Why is the multiplier usage always zero when targeting Virtex-II/-II Pro, Spartan-3/E/A? See (Xilinx Answer 24437).

- Why are my results incorrect when I use the Radix-2 Lite implementation, with the block floating point option? See (Xilinx Answer 24463).

LogiCORE FIR Compiler v3.0

- I cannot use the multi-column support when my coefficients are symmetrical. See (Xilinx Answer 22936).

- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. See (Xilinx Answer 5366).

- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).

- Why does FIR Compiler, Floating Point Operator, and Fast Fourier Transform error out when attempting to customize them on Solaris? See (Xilinx Answer 24317).

- Distributed Arithmetic Filter Architecture:

-- CORE Generator memory consumption issues occur with the DA FIR. See (Xilinx Answer 18663).

-- Half-band output width behavioral model does not match the netlist output width. See (Xilinx Answer 21414).

-- Interpolating half-band fails to check for zeros in coefficients. See (Xilinx Answer 20840).

- Multiply Accumulator Filter Architecture for all devices other than Virtex-4 and Virtex-5:

-- Why does my single-rate MAC FIR filter fail to generate, giving me an empty or missing netlist and "ERROR:sim - NgdBuild:153" or "ERROR:NgdBuild:604"? See (Xilinx Answer 22706).

-- Information on support for multiple MAC FIRs with different COE files in the same project. See (Xilinx Answer 16433).

-- Back-annotated Verilog simulation causes memory collision errors. See (Xilinx Answer 16106).

-- COE errors reported in wrong format. See (Xilinx Answer 14202).

-- Some bitwidths fail to allow core to implement. See (Xilinx Answer 20307).

LogiCORE Multiplier Generator v10.0

- Why does my Virtex-5 LUT-based multiplier give incorrect output results in post-MAP simulation, post-PAR simulation, and hardware when I do not use any pipelining? See (Xilinx Answer 23705).

- How do I dynamically control the sign of my A port input, or why can I no longer use the a_signed input to control the sign of my A data input? See (Xilinx Answer 23599).

- Why can I not add handshaking signals to my multiplier? See (Xilinx Answer 23598).

- How do I generate a multiplier with an asynchronous clear? See (Xilinx Answer 23600).

Known Issues in Existing IP

LogiCORE Add Sub v7.0

- Why is my output result one less than the expected result? See (Xilinx Answer 23933).

LogiCORE CIC v3.0

- The CIC Filter v3.0 exhibits overflow for inputs that use the complete dynamic bit range of the data input. See (Xilinx Answer 12480).

- The CIC Filter v3.0 reset. See (Xilinx Answer 20187).

- The CIC Filter v3.0 input and output date format. See (Xilinx Answer 17210).

LogiCORE Complex Multiplier v2.1

- Spartan-3E support for the Complex Multiplier. See (Xilinx Answer 21467).

LogiCORE CORDIC v3.0

- Output does not change when the output width is larger than 12 bits. See (Xilinx Answer 20371).

- LogiCORE CORDIC v3.0 - Why does the behavioral simulation for the CORDIC square root mode require four extra clocks after asserting the ND signal before the data will be processed? See (Xilinx Answer 23934).

LogiCORE Distributed Arithmetic FIR (DA FIR) Filter v9.0

- CORE Generator memory consumption issues occur with the DA FIR. See (Xilinx Answer 18663).

- Half-band output width behavioral model does not match the netlist output width. See (Xilinx Answer 21414).

- Interpolating half-band fails to check for zeros in coefficients. See (Xilinx Answer 20840).

- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. See (Xilinx Answer 5366).

- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).

LogiCORE Digital Down Convertor (DDC)

- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. See (Xilinx Answer 5366).

- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).

LogiCORE DDS Compiler v1.1

- Why is the behavioral simulation output incorrect when using the structural simulation model? See (Xilinx Answer 24316).

- Why are the outputs on the DDS CORE Generator GUI always displayed as 32-bits wide? See (Xilinx Answer 24410).

- Why are the outputs on the DDS schematic symbol always displayed as 32-bits wide? See (Xilinx Answer 24412).

LogiCORE 1024-pt FFTv1.0

- The block RAM configurations in the FFT/IFFT data sheet do not match the hardware configurations. See (Xilinx Answer 15311).

LogiCORE 16-pt FFT v2.0

- The slice utilization of a 16-point Virtex FFT is greater than that of a 64-point FFT. See (Xilinx Answer 8765).

LogiCORE 256-pt FFT v2.0

- The FFT for a Virtex-II device causes PAR warnings and errors. See (Xilinx Answer 13173).

LogiCORE 32-pt FFT v1.0

- A Verilog model is not available for the FFT Core. See (Xilinx Answer 11155).

LogiCORE 64-pt FFT v2.0

- The RESULT signal is not reset properly in the 64-point FFT v2.0. See (Xilinx Answer 15383).

LogiCORE FFT

- Simulation of all fixed netlist FFT (64, 256, 1024) Cores generates many warnings. See (Xilinx Answer 14861).

- Information on output connections to the fixed netlist FFT (64, 256, 1024) Cores during a write operation to RAM X (TMS configuration). See (Xilinx Answer 9288).

LogiCORE Fast Fourier Transform (xFFT) v3.2/patch 1

- Large FFT point size generation times. See (Xilinx Answer 21988).

- Some bitwidths fail to allow core to implement. See (Xilinx Answer 20307).

- First frame after multi-cycle reset might be incorrectly marked as valid. See (Xilinx Answer 24436).

LogiCORE Floating-Point Operators v3.0

- Why do I not see a resource estimation graph for my Floating Point operator function? See (Xilinx Answer 24039).

- Why does FIR Compiler, Floating Point Operator, and Fast Fourier Transform error out when I attempt to customize them on Solaris? See (Xilinx Answer 24317).

LogiCORE MAC v4.0

- Virtex-4 maximum number of cycles. See (Xilinx Answer 21511).

- When I set up my Multiply Accumulate v4.0 Core to have a wide input (e.g., 24x16) and use an output that is less than full precision, why is there no activity on the output of my core during simulation? See (Xilinx Answer 24096).

LogiCORE MAC FIR v5.1

- Information on support for multiple MAC FIRs with different COE files in the same project. See (Xilinx Answer 16433).

- Back-annotated Verilog simulation causes memory collision errors. See (Xilinx Answer 16106).

- COE Errors reported in wrong format. See (Xilinx Answer 14202).

- Some bitwidths fail to allow core to implement. See (Xilinx Answer 20307).

- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. See (Xilinx Answer 5366).

- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).

LogiCORE Pipelined Divider v3.0

- How to do I perform a Verilog behavioral simulation? See (Xilinx Answer 20615).

LogiCORE RAM-based Shift Register v9.0

- Large RAM-based Shift Registers fail to generate. See (Xilinx Answer 21410).

- Why is the LogiCORE RAM-based Shift Register v9.0 almost 10 times larger than the LogiCORE RAM-based Shift Register v8.0, when targeting Virtex or Spartan-II? See (Xilinx Answer 23696).

LogiCORE Turbo Product Code Encoder and Decoder (TPC)

- How can I get the TPC to compile using XST, without incurring MAP Pack error: "ERROR:Pack:679"? See (Xilinx Answer 22258).

- Why does the reset need to be applied for the code to be changed? See (Xilinx Answer 24298).

- Why does the OutputRDY signal Remain high for six clock cycles after the output FIFO is empty? See (Xilinx Answer 24299).

AR# 24435
Date Created 09/04/2007
Last Updated 06/09/2010
Status Archive
Type General Article