We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24465

Project Navigator - Hierarchy is not correctly displayed for HDL files > 1 Mbyte


Designs containing large source files (> 1 MB) might not have the hierarchy displayed correctly in Project Navigator.


If the HDL file sizes of a design are larger than 1 MB and the hierarchy is not being displayed correctly, please try the following to work around this issue:


Create a new environment variable named Xilinx_DU_REDUCTION_SIZE and set the value to a value greater than the file size in bytes. For example, if an HDL source of 2 MB in size is showing this problem, setting Xilinx_DU_REDUCTION_SIZE to 2097153 or higher will solve the hierarchy issue.


The display issue arises as a side effect of an intentional hierarchy optimization for System Generator designs. System Generator sources are typically large in size and contain few top-level design units and then lots of lower-level design units which (by assumption) are not important to customers. Therefore, disabling the generation of these lower-level design units (DUs) improves the performance of Project Navigator.

In order to disable generation and display of these lower-level DUs, a check was implemented that looks for the source file size, and if the file size is greater than a certain size (by default 1000000 bytes, or close to 1 MB), and then only generates the top-level DUs and ignores the lower-level modules. The default size threshold mentioned here can be altered using the environment variable Xilinx_DU_REDUCTION_SIZE.
AR# 24465
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked