PlatGen issues a segmentation fault message for my design soon after running the clock DRCs:
"Check port drivers...
Performing Clock DRCs...
gmake: *** [implementation/ppc405_0_wrapper.ngc] Segmentation fault
ERROR:MDT - Error while running "gmake -f system.make netlist""
To work around this issue, remove the "CLK_FREQ" sub-property on the external clock ports in the MHS file.
The problem is fixed in the next major release of the design tools.