UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24486

Virtex-5 - What are the addresses and values for dynamic reconfiguration of the DCM or PLL through the DRP?

Description

The Virtex-5 FPGA User Guide does not contain information on the correct addresses and values for dynamic reconfiguration of the DCM or the PLL. Where can I find the reconfiguration memory addresses and valid values?

Solution

DCM DRP information has been added to the Virtex-5 FPGA Configuration Guide (UG191).

PLL DRP information is available in a spreadsheet:
http://www.xilinx.com/txpatches/pub/applications/misc/pll_drp_2_0.zip
AR# 24486
Date Created 09/04/2007
Last Updated 02/20/2013
Status Active
Type General Article
Devices
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Less
IP
  • Digital Clock Manager (DCM) Module
  • PLL Module