Basic UCF Syntax Examples for Timing Specifications
PERIOD TIME-SPEC
The PERIOD specification covers all timing paths that start or end at a register, latch, or synchronous RAM that are clocked by the reference net (excluding pad destinations). It also covers the setup requirement of the synchronous element relative to other elements (e.g., flip-flops, etc.).
NOTE: The default unit for time is nanoseconds.
NET clk20MHz PERIOD = 50 ; NET clk50mhz TNM = registers_50mhz ; TIMESPEC TS01 = PERIOD registers_50mhz 20 ;
FROM:TO TIME-SPECs
FROM:TO style time specs can be used to constrain paths between time groups.
NOTE: The keywords RAMS, FFS, PADS, and LATCHES are predefined time groups used to specify all elements of each type in a design.
TIMESPEC TS02 = FROM : PADS : TO : FFS : 36 ; TIMESPEC TS03 = FROM : FFS : TO : PADS : 36 ns ; TIMESPEC TS04 = FROM : PADS : TO : PADS : 66 ; TIMESPEC TS05 = FROM : PADS : TO : RAMS : 36 ; TIMESPEC TS06 = FROM : RAMS : TO : PADS : 35.5 ;
NOTE: The predefined time groups LATCHES and RAMS are not applicable to CPLD designs.
To automatically include clock buffer/routing delay in your "PADS:TO:<synchronous element> or <synchronous element>:TO:PADS timing specifications, use OFFSET constraints instead of FROM:TO constraints.
For an input where the maximum clock-to-out (Tco) of the driving device is 10 ns:
NET in_net_name OFFSET = IN : 10 : AFTER : clk_net_name ;
For an output where the minimum setup time (Tsu) of the device being driven is 5 ns:
NET out_net_name OFFSET = OUT : 5 : BEFORE : clk_net_name ;
TIMING IGNORE
If the timing of paths can be ignored, use Timing Ignore (TIG).
NOTE: You can use the "*" character as a wild card for bus names. You can use a "?" character as a one-character wild card.
To ignore timing of net "reset_n":
NET : reset_n : TIG ;
To ignore data_reg(7:0) net in instance "mux_mem":
NET : mux_mem/data_reg* : TIG ;
To ignore data_reg(7:0) net in instance "mux_mem" as related to a TIMESPEC named TS01 only:
NET : mux_mem/data_reg* : TIG = TS01 ;
To ignore "data1_sig" and "data2_sig" nets:
NET : data?_sig : TIG ;
PATH EXCEPTIONS
If your design contains outputs that can be slower than others, you can create specific TIMESPECs similar to this example for output nets named "out_data(7:0)" and "irq_n":
If multi-cycle FF-to-FF paths exist, you can create a time group using either the TIMEGRP or TNM statements.
WARNING: Many VHDL/Verilog synthesizers do not predictably name flip-flop Q output nets. However, most synthesizers do assign predictable instance names to flip-flops.
NOTE: The Mode pins (MD0, MD1, MD2) and the Boundary Scan pins [TCK, TDI, TDO, TMS] cannot be prohibited or assigned; an error might occur if these sites are prohibited from the UCF file. These sites are reserved sites and are used only if specified in the design.
Assigning Specific Logic Locations
Place 0.
A basic element (BEL) in a specific CLB. BEL = FF, LUT, RAM, etc.:
INST io_buf_name LOC = P110 ; INST instance_path/BEL_name LOC = CLB_R17C36 ;
Assigning Area Constraints
XC3000 - Place CLB logic anywhere in the top-left corner of the device bounded by Row F and Column F:
INST logic_name LOC=AA:FF ;
XC4000 - Place logic in the top-left corner of the device in a 5x5 area bounded by Row 5 and Column 5:
INST logic_name LOC=CLB_R1C1:CLB_R5C5 ;
XC4000, XC5200 - Place a BUFT anywhere in the area bounded by Row 1, Column 1 and Row 2, Column 8:
INST logic_name LOC=TBUF_R1C1:TBUF_R2C8 ;
XC5200 - Place logic in any slice in the top-left corner of the device bounded by Row 4, Column 4:
INST logic_name LOC=CLB_R1C1.LC3:CLB_R4C4..LC0 ;
Multiple LOC constraint examples:
XC4000 - Place a decoder on the top or bottom edge:
INST logic_name LOC=T,B ;
XC4000, Virtex, Spartan - Place CLB logic in the top-left corner of the device in a 5x5 area, but not in the CLB, in Row 5, Column 5: