This Release Note is for the System Monitor Wizard v1.0 released in 9.1i IP Update 1 and contains the following:
- General Information
- New Features
- Bug Fixes
- Known Issues
The System Monitor Wizard v1.0 supports the Virtex-5 family. The Wizard can be used to customize the I/O Ports usage, the User Alarms and Thresholds, and the Channel Sequencer. For more information on these features, refer to the "System Monitor User Guide", accessible at:
New Features in v1.0
This is the first release of the System Monitor Wizard. The Wizard has been developed to help you customize the System Monitor primitive.
Bug Fixes in v1.0
This is a new core and there are no bug fixes.
1 The intended functionality of the System Monitor dictates that if "Event Mode Timing" is used, it is not possible to increase the acquisition time using the ACQ bit. In Event Timing Mode, you initiate the conversion cycle by using CONVST or CONVSTCLK, which allows more control over the acquisition time if required. It is also not possible to use Event Mode timing with the Channel Sequencer.
There is a known issue in the System Monitor Wizard v1.0 if "Event Mode Timing" is selected and the "Use Channel Sequencer" mode is selected at startup, then the Timing Mode is correctly changed to "Use Continuous Mode". However, the "Increase Acquisition Time" checkbox remains incorrectly grayed out. To work around this issue, close the Wizard and reopen, and then select the Startup Channel Selection before the Timing Mode.
2 On Linux platforms, the Increase Acquisition Time checkbox turns red when selected (this is a GUI issue).
On Linux platforms, if "Increase acquisition time" is selected, and "Enable DCLK" is subsequently selected and deselected, some of the text in the GUI turns red and the clock divider value is incorrect. To reset this to the correct value, deselect and reselect Increase acquisition time.
3 On all platforms for some DCLK and ADC conversion rates, the Wizard generates the following warning:
"WARNING:sim:192 - Xco Parameter changed from X to Y during Recustomization."
The clock divider ratio must be greater than eight. DCLK can be in the range of 1 - 250 MHz and the ADC conversion rate (kSPS) can be in the range of 20 - 200 kSPS. Clock divider ratio = DCLK /(26 * ADC conv rate). Note the 26 must be replaced with 32 if the Increase acquisition time is checked.
The Wizard is currently producing an erroneous warning indicating that the divider value is incorrect and resetting the DCLK and ADC conversion rate to the default. To work around this issue, perform the following:
1. Perform the calculation by hand.
2. Change config register 2 (@ addr 42h by changing INIT_42 parameter) to the desired value in the ".vhd" or ".v" file created by the Wizard.
3. Instantiate the SYSMON in your design using the contents of the ".vhd" or ".v" file (instead of the ".xco" file).>
4 The System Monitor Wizard generated HDL code does not contain a placeholder for the SIM_MONITOR_FILE attribute. The SIM_MONITOR_FILE is used to provide the analog stimulus in a simulation. To work around this issue instantiate the SYSMON in your design using the contents of the ".vhd" or ".v" file (instead of the ".xco" file) and manually change SIM_MONITOR_FILE value.
5 In the System Monitor Wizard GUI if the VN and VP pins are selected there was a known issue that the pins remained tied to ground in the wrapper file is output.
To work around this issue instantiate the SYSMON in your design using the contents of the ".vhd" or ".v" file (instead of the ".xco" file) and manually change the code to add the VP and VN ports to ports on the toplevel of the ".vhd" or ".v" file.
6. The System Monitor Wizard is missing from the FPGA Features and Design list in 11.3 CoreGEN. See Xilinx Answer Record #3349.