The SYSTEM_JITTER constraint is used to represent the power noise, board noise, and any extra jitter of the overall system.
To include the clock edge noise and power noise into the constraint value, two measurements should be performed:
With these, the SYSTEM_JITTER should then be Vn*(T2 - T1)/(Virtex_FPGA-V1)
A suggested SYSTEM_JITTER value is 300 ps. The default SYSTEM_JITTER value for many device families are between 50-70 ps.