In my SW application, I enable the PowerPC to the wait state. According to the PowerPC reference guide, the PowerPC continues to respond to interrupts and be can be restarted through the use of external interrupts and timer interrupts. However, in my case, the PowerPC goes back to the wait state after returning from interrupt.
I have been debugging this and found out that because of the context switching in the Xilinx implementation the old machine states are copied back into the SRR1 and MSR register. As a result, the PowerPC will always remain in the wait state even if I clear the SRR1 [WE] bit in the interrupt handler routine. Do I need to modify the Xilinx vector handler table to change this context switching behavior in Xilinx's BSP?