This Answer Record contains the Release Notes for the LogiCORE Fibre Channel Arbitrated Loop v2.1Core, which was released in 9.1i IP Update #1, and includes the following:
- New Features
- Bug Fixes
- Known Issues
For installation instructions and design tools requirements, see (Xilinx Answer 24307).
In version 2.1, support for CES4 Virtex-4 FX devices replaces support for CES2 and CES3 devices with the use of a new calibration block.
- Fixes for CR 225194, CR 228392, CR 230769, CR 230590,
CR 230589, CR 230587, CR 230585, CR 230583, CR 230581, CR 230579,
CR 230578, CR 224701, CR 230586, CR 233046, CR 233130, CR 423714,
CR 423720, CR 428419, CR 423715, CR 423716, CR 423717, CR 423719.
- Additional pins introduced:
REQ_DEFAULT_INIT Input - Drive this High to skip the Loop Initialization phase and adopt Preferred AL_PA.
MGT_RXCHARISCOMMA [1:0] Input - Drive this from the similarly-named MGT/GT11 outputs.
- Support for Virtex-5 devices added.
Known Issues in v1.1
-For Virtex-II Pro board designs to avoid BER failures, it is important to insure that board meets Virtex-II Pro MGT specifications. For more information, see (Xilinx Answer 25035).