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AR# 24602

LogiCORE Endpoint PIPE v1.6 and v1.6.1 for PCI Express - Release Notes and Known Issues for 9.1i IP Update 1 (9.1i_IP1) and 9.1i IP Update 2 (9.1i_IP2)

Description

This Release Notes and Known Issues Answer Record is for the LogiCORE Endpoint PIPE v1.6 for PCI Express released in 9.1i IP Update 1 and 9.1i IP Update 2, and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 24307).

Solution

General Information

IMPORTANT NOTE: 9.1i IP Update 2 is a cumulative IP Update release. However, the LogiCORE Endpoint PIPE v1.6 for PCI Express was not updated in IP Update 2. Consequently, the same core exists in both IP Update 1 and IP Update 2. As a result, if you have installed the v1.6.1 patch, you must reinstall it after installing the 9.1i IP Update 2.

A patch update (v1.6.1) is available for the pci_exp_1_lane_epipe_ep Core. To install this patch, you must first install the 9.1i IP Update 1 CORE Generator update. This must be downloaded and installed on top of the current ISE 9.1i sp2 design tools. For general information on this update, see (Xilinx Answer 24307). This update is found at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

Once the IP Update has been installed, download the patch at:

http://www.xilinx.com/txpatches/pub/swhelp/coregen/pci_express_91i_ip_update_1_rev1.zip

To install this v1.6.1 patch update, unzip the file into your current Xilinx install directory, as pointed to by your Xilinx environment variable. You might be prompted to allow the update to overwrite existing files; select "Yes to All."

Interrupt Interface Changes

The LogiCORE Endpoint for PCI Express v1.6 has an enhanced interrupt interface that supports multivector MSI and multiple legacy interrupt messages. Designs migrating from v1.5 will require port changes to the core interface and logic changes to control the new interface. Please refer to the User Guide that is delivered with the core for more information on using the new interface.

New Features

- Added Spartan-3A Support

- Added Multivector MSI

- Legacy Interrupt now supports INTB, INTC and INTD

Bug Fixes

-CR 427097: Core no longer sends spurious Enter-L1 DLLP immediately after recovery from L1 to L1

-CR 430740: I/O BAR size can be selected down to 16 bytes

-CR 425746: When extended configuration space is enabled, the TLM allows the user application to transmit when in a non-D0 state

Known Issues

- Refer to the "readme_pci_express_pipe.txt" file delivered with the core for known issues at the time of the release.

-Refer to the NXP data sheet for PX1011B errata items. PX1011B errata items are included in section 14 of the data sheet.

This data sheet is available at:

http://www.nxp.com/acrobat_download/datasheets/PX1011B_4.pdf
NXP Product Page:

http://www.nxp.com/#/pip/pip=[pip=PX1011B_4]|pp=[t=pip,i=PX1011B_4]

(Xilinx Answer 24952) - LogiCORE Endpoint PIPE for PCI Express v1.6.1 - 9.1i SP2 Timing Analyzer GUI displays "Unexpected Error in index generation process near line 326 Offending index line is "2 353"

Revision History

9/22/2009 - Added reference to NXP data sheet.

AR# 24602
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article