We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24639

LogiCORE Cascaded Integrator-Comb (CIC) Filter v3.0 - What is the latency of the first valid RDY signal for a decimation filter?


In a CIC v3.0 decimation filter, the RDY signal incorrectly asserts the same clock cycle when the first asserted ND is latched. RDY will continue to assert at a constant interval of latched High ND signals (equal to the decimation rate) until the output of the filter is valid and the "real" RDY signal occurs.


To work around this issue, create user control logic to ignore the false RDY signals until the number of clocked High ND signals, described by the following equation, have passed:

For a decimating CIC:

Latency between first input and first valid output = (stages + 1) * (decimation rate) * (channels) + pipeline stages (if used)

For an interpolating CIC:

Latency between first input and first valid output = ((stages * interpolation_rate) + (stages + 1))*(channels) + pipeline stages (if used)

where in the CIC GUI:

stages = Number of Stages

decimation rate = Sample Rate

channels = Number of Channels

AR# 24639
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked