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AR# 24666

LogiCORE Direct Digital Synthesis (DDS) Compiler v1.1 - Why do the outputs not go to zero when the SCLR signal is asserted, or why are the behavioral simulation outputs X when the SCLR signal is asserted?

Description

Why do the outputs not go to zero when the SCLR signal is asserted, or why are the behavioral simulation outputs X when the SCLR signal is asserted?

Solution

The data sheet states that the output will go to zero when the SCLR signal is asserted. This is not correct. When SCLR is asserted, the outputs are undefined, just as is shown when a behavioral simulation is run. The documentation will be updated in the Direct Digital Synthesis (DDS) Compiler v2.0 Data Sheet.

AR# 24666
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article