The Virtex-4 FPGA User Guide (UG070) indicates IDELAYCTRL can be instantiated with or without location (LOC) constraints.
When the IDELAYCTRL is instantiated with location constraints (e.g., "INST .idelayctrl_instance_name. LOC = IDELAYCTRL_XnYm"), how can the location coordinates of it be determined?
An IDELAYCTRL module exists in an I/O column in every clock region. An IDELAYCTRL module calibrates all the IDELAY modules within its I/O Bank.
The exact location coordinates of an IDELAYCTRL can also be found in the PlanAhead tool. Following is a set of detailed steps on how to find IDELAYCTRLs in the PlanAhead tool:
1. Open a design in thePlanAhead tool.
2. In the package view, click on the desired pin.
3. In the device view, zoom in on the area of the highlighted pin.
4. Scroll the pointer over the IDELAYCTRL (located on the left side of the nearest red box; see picture).
Using FPGA Editor and PACE together helps to determine which IDELAYCTRL should be used and the location coordinates of it.
Some Xilinx customers prefer to use an outside tool (ADEPT) to generate this location information:
NOTE: This tool is not supported by Xilinx.