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AR# 24709

9.1 - ISE Simulator - Divide by zero error when simulating the Virtex-5 PLL


When I try to simulate the Virtex-5 PLL in the ISE Simulator with the simulation language set to VHDL, I get the following error:

Simulator is doing circuit initialization process.

ERROR:Simulator:29 - at 0 ns : Divide by zero error

Simulation stopped when executing process: unisim_VITAL.vhd:CLOCK_PERIOD_UPDATE_P

on line 124 in file "C:/temp/ge_pll/pll.vhd"


This issue is fixed in 9.2sp1.

AR# 24709
Date 07/22/2010
Status Archive
Type General Article
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