We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24726

9.1i XST - The Virtex-5 PCIE_EP block delays are not available in XST, which leads to incorrect optimizations


The XST compiler in 9.1 does not contain timing information for the PCIE Block. Because of this, the optimizations on paths leading to or from the PCIE block are not optimal. This can lead to difficulties in the implementation tools.


This issue has been fixed in ISE 9.1 Service Pack 2.

AR# 24726
Date 05/21/2014
Status Archive
Type General Article
Page Bookmarked