Change the FSL_V20 v2.00a component to allow the coincident setting of the parameters C_ASYNC_CLKS = 1 and C_IMPL_STYLE = 1.
This combination provides a block RAM-based Async FIFO inside the FSL_V20 component and provides the following benefits:
- deeper asynchronous FIFOs in an FSL
- less challenging routing requirements since the SRLs are avoided
The block RAM implementation of FIFO is completed in EDK 9.1i, available at: